DDRPHY/LPDDRR/HBM IP Design Engineer

Description

Summary: Join an experienced testchip team developing in leading-edge technology, focusing on DDRPHY/LPDDRR/HBM test chip design and full silicon development flow. Highlights: 1. Developing in leading-edge technology within an experienced testchip team 2. Involved in full silicon development flow including RTL design and lab bring-up 3. Focus on high-speed design, timing closure, and complex hardware debugging **Date posted** 04/12/2026 ### **Category** **Engineering****Hire Type** **Employee****Job ID** **16936****Remote Eligible** **No****Date Posted** **04/12/2026** In this role you will be joining an experienced testchip team developing in leading\-edge technology. The group is designing DDRPHY/LPDDRR/HBM test chip and also includes HBM design/verification. You will join in the full silicon development flow including RTL design/verification/Synthesis/DFT/LAB bring\-up etc. Key Qualifications A history of excellent problem\-solving skills Clear communication both written and oral Highspeed design and timing closure Designing RTL with SystemVerilog and Verilog Capable of automating repetitive tasks using a variety of scripting languages 1\+ years of experience in RTL design or verification, including interfacing with Mixed Signal Designs Interfacing with Analog and Mixed Signal designs Writing clear specification documents Experience of entire ASIC and IP development flow Aware of DFT/DFM flows Experience of debugging complex hardware issues Preferred Experience Interfacing with Mixed Signal Designs Capable of modeling Analog and Mixed Signal Circuits Capable of setting up and debugging physically aware synthesis DDR and HBM DRAM technologies At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.